imx6dl在eMMC启动方式启动时uboot阶段卡死问题请教？
希望懂uboot的大神们进来看看，指教下我这个问题下面该如何调试。谢谢！imx6dl在eMMC启动方式启动时uboot阶段卡死时串口输出信息如下：
U-Boot 2009.08 ( 4月 23 2018 - 14:58:15)
CPU: Freescale i.MX6 family TO1.3 at 792 MHz
Temperature: 53 C, calibration data 0x5944f17d
mx6q pll1: 792MHz
mx6q pll2: 528MHz
mx6q pll3: 480MHz
mx6q pll8: 50MHz
ipg clock : 66000000Hz
ipg per clock : 66000000Hz
uart clock : 80000000Hz
cspi clock : 60000000Hz
ahb clock : 132000000Hz
axi clock : 198000000Hz
emi_slow clock: 99000000Hz
ddr clock : 396000000Hz
usdhc1 clock: 198000000Hz
usdhc2 clock: 198000000Hz
usdhc3 clock: 198000000Hz
usdhc4 clock: 198000000Hz
nfc clock : 24000000Hz
Board: i.MX6DL/Solo-SABRESD: unknown-board Board: 0x61013
Boot Device: SD
I2C: ready
DRAM: 2 GB
MMC: FSL_USDHC: 0,FSL_USDHC: 1,FSL_USDHC: 2,FSL_USDHC: 3
板子是自己做的板子，参考的是OKMX6X-S3（imx6dl）的开发板。
eMMC芯片型号是MT29F128G08，eMMC接在SDHC3上。
1、使用mfgtools工具已经将uboot和rootfs烧写成功了，但是在启动的时候卡在了上面输出；
2、经过自己在uboot中添加打印输出信息发现其卡在了eMMC模块处理部分，具体函数流程如下：
mmc_startup->
init_part->test_part_dos->mmc_bread->mm_send_cmd->esdhc_send_cmd时在while (!(readl(®s->irqstat) & IRQSTAT_BRR))；
处进入死循环；
说明：eMMC的product已经读取到了，并且跟手册上的描述一致。
3、在while (!(readl(®s->irqstat) & IRQSTAT_BRR))；前打印输出SDHC3相关寄存器如下：
CMD_SEND:17
ARG 0x00000000
FLAG 0
regs->dsaddr = 02198000, value=0x0 -----print_sdhc3_regs--165
regs->blkattr = 02198004, value=0x10200 -----print_sdhc3_regs--166
regs->prsstat = 02198024, value=0xff8d820e -----print_sdhc3_regs--167
regs->proctl = 02198028, value=0x8800024 -----print_sdhc3_regs--168
regs->sysctl = 0219802c, value=0x8e0018 -----print_sdhc3_regs--169
regs->irqstat = 02198030, value=0x0 -----print_sdhc3_regs--170
regs->irqstaten = 02198034, value=0x157f513f -----print_sdhc3_regs--171
regs->irqsigen = 02198038, value=0x0 -----print_sdhc3_regs--172
regs->autoc12err = 0219803c, value=0x0 -----print_sdhc3_regs--173
regs->hostcapblt = 02198040, value=0x7f30000 -----print_sdhc3_regs--174
regs->wml = 02198044, value=0x8000880 -----print_sdhc3_regs--175
regs->mixctrl = 02198048, value=0x18 -----print_sdhc3_regs--176
regs->dllctrl = 02198060, value=0x1000001 -----print_sdhc3_regs--177
regs->dllstatus = 02198064, value=0x3a07 -----print_sdhc3_regs--178
regs->clktunectrlstatus = 02198068, value=0x0 -----print_sdhc3_regs--179
regs->vendorspec = 021980c0, value=0x20007809 -----print_sdhc3_regs--180
regs->mmcboot = 021980c4, value=0x0 -----print_sdhc3_regs--181
regs->hostver = 021980fc, value=0x103 -----print_sdhc3_regs--182开发板在此处寄存器的值如下：
regs->dsaddr = 0219c000, value=0x0 -----print_sdhc3_regs--165
regs->blkattr = 0219c004, value=0x10200 -----print_sdhc3_regs--166
regs->prsstat = 0219c024, value=0xff8d8a8a -----print_sdhc3_regs--167
regs->proctl = 0219c028, value=0x8800024 -----print_sdhc3_regs--168
regs->sysctl = 0219c02c, value=0x8e0018 -----print_sdhc3_regs--169
regs->irqstat = 0219c030, value=0x20 -----print_sdhc3_regs--170
regs->irqstaten = 0219c034, value=0x157f513f -----print_sdhc3_regs--171
regs->irqsigen = 0219c038, value=0x0 -----print_sdhc3_regs--172
regs->autoc12err = 0219c03c, value=0x0 -----print_sdhc3_regs--173
regs->hostcapblt = 0219c040, value=0x7f30000 -----print_sdhc3_regs--174
regs->wml = 0219c044, value=0x8000880 -----print_sdhc3_regs--175
regs->mixctrl = 0219c048, value=0x18 -----print_sdhc3_regs--176
regs->dllctrl = 0219c060, value=0x1000001 -----print_sdhc3_regs--177
regs->dllstatus = 0219c064, value=0x3c07 -----print_sdhc3_regs--178
regs->clktunectrlstatus = 0219c068, value=0x0 -----print_sdhc3_regs--179
regs->vendorspec = 0219c0c0, value=0x20007809 -----print_sdhc3_regs--180
regs->mmcboot = 0219c0c4, value=0x0 -----print_sdhc3_regs--181
regs->hostver = 0219c0fc, value=0x3 -----print_sdhc3_regs--182发现在有如下几个寄存器不同之处：
1）uSDHCx_PRES_STATE
a)bit
Buffer Read Enable
This status bit is used for non-DMA read transfers. The uSDHC implements an internal buffer to transfer
data efficiently. This read only flag indicates that valid data exists in the host side buffer. If this bit is high,
valid data greater than the watermark level exist in the buffer. A change of this bit from 1 to 0 occurs when
some reads from the buffer(read DATPORT (Base + 0x20)) are made and the buffer hasn't valid data
greater than the watermark level. A change of this bit from 0 to1 occurs when there is enough valid data
ready in the buffer and the Buffer Read Ready interrupt has been generated and enabled.
1 Read enable
0 Read disable
b)bit
SD Clock Gated Off Internally
This status bit indicates that the SD Clock is internally gated off, because of buffer over / under-run or read
pause without read wait assertion, or the driver set FRC_SDCLK_ON bit is 0 to stop the SD clock in idle
status. Set IPG_PERCLK_SOFT_EN and CARD_CLK_SOFT_EN to 0 also gate off SD clock. This bit is
for the Host Driver to debug data transaction on the SD bus.
1 SD Clock is gated off.
0 SD Clock is active
c)bit
1 DATA Line Active
0 DATA Line Inacti
2)uSDHCx_INT_STATUS
a)bit
Buffer Read Ready
This status bit is set if the Buffer Read Enable bit, in the Present State register, changes from 0 to 1. Refer
to the Buffer Read Enable bit in the Present State register for additional information.
1 Ready to read buffer
0 Not ready to read buffer
发现有问题的板子刚好跟开发板在上面的位相反。
故想请教下，mmc_startup->
init_part->test_part_dos->mmc_bread->mm_send_cmd->esdhc_send_cmd这个函数流程具体作用是干什么的？然后这个问题可通过什么方式来进行下一步的调试。
谢谢！
您好
您对核心板有做过什么改动吗，另外我给您找了一篇有关您咨询函数的文章您可以看一看https://blog.csdn.net/zzobin/article/details/7688705
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