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注册时间2021-6-21
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使用的TFA源码为NXP开源的。
地址为:https://source.codeaurora.org/external/qoriq/qoriq-components/atf
INFO: RCW BOOT SRC is SD/EMMC
INFO: RCW BOOT SRC is SD/EMMC
INFO: esdhc_emmc_init
INFO: Card detected successfully
INFO: init done:
INFO: platform clock 600000000
INFO: DDR PLL1 2100000000
INFO: DDR PLL2 0
INFO: time base 38 ms
INFO: Parse DIMM SPD(s)
INFO: cal cs
INFO: cs_in_use = 1
INFO: cs_on_dimm[0] = 1
NOTICE: Fixed DDR on board
INFO: Time after parsing SPD 13 ms
INFO: Synthesize configurations
INFO: cs 0
INFO: odt_rd_cfg 0x0
INFO: odt_wr_cfg 0x4
INFO: odt_rtt_norm 0x3
INFO: odt_rtt_wr 0x0
INFO: auto_precharge 0
INFO: ctlr_init_ecc 1
INFO: x4_en 0
INFO: ap_en 0
INFO: ctlr_intlv 0
INFO: ctlr_intlv_mode 0
INFO: ba_intlv 0x0
INFO: data_bus_used 0
INFO: otf_burst_chop_en 1
INFO: burst_length 0x6
INFO: dbw_cap_shift 0
INFO: Assign binding addresses
INFO: ctlr_intlv 0
INFO: rank density 0x80000000
INFO: CS 0
INFO: base_addr 0x0
INFO: size 0x80000000
INFO: base 0x0
INFO: Total mem by assignment is 0x80000000
INFO: Calculate controller registers
INFO: Skip CL mask for this speed 0x4000
INFO: Skip caslat 0x4000
INFO: cs_in_use = 0x1
INFO: cs0
INFO: _config = 0x80040312
INFO: cs[0].bnds = 0x7f
INFO: sdram_cfg[0] = 0xe5000000
INFO: sdram_cfg[1] = 0x401150
INFO: sdram_cfg[2] = 0x0
INFO: timing_cfg[0] = 0xd1770018
INFO: timing_cfg[1] = 0xf2fc8245
INFO: timing_cfg[2] = 0x594197
INFO: timing_cfg[3] = 0x2161100
INFO: timing_cfg[4] = 0x220002
INFO: timing_cfg[5] = 0x5401400
INFO: timing_cfg[6] = 0x0
INFO: timing_cfg[7] = 0x26600000
INFO: timing_cfg[8] = 0x5446a00
INFO: timing_cfg[9] = 0x0
INFO: dq_map[0] = 0x5b65b658
INFO: dq_map[1] = 0xd96d8000
INFO: dq_map[2] = 0x0
INFO: dq_map[3] = 0x1600000
INFO: sdram_mode[0] = 0x3010631
INFO: sdram_mode[1] = 0x100200
INFO: sdram_mode[9] = 0x8400000
INFO: sdram_mode[8] = 0x500
INFO: interval = 0x1ffe0000
INFO: zq_cntl = 0x8a090705
INFO: ddr_sr_cntr = 0x0
INFO: clk_cntl = 0x2000000
INFO: cdr[0] = 0x80040000
INFO: cdr[1] = 0xc1
INFO: wrlvl_cntl[0] = 0x86750609
INFO: wrlvl_cntl[1] = 0xa0b0c0d
INFO: wrlvl_cntl[2] = 0xf10110e
INFO: debug[28] = 0x61
INFO: Time before programming controller 182 ms
INFO: Program controller registers
INFO: total size 2 GB
INFO: Need to wait up to 480 ms
ERROR: Found training error(s): 0x2100
ERROR: Error: Waiting for D_INIT timeout.
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
NOTICE: Incorrect DRAM0 size is defined in platfor_def.h
ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/xlat_tables_internal.c:753
使用的DDR配置参数
struct dimm_params ddr_raw_timing = {
.n_ranks = 1,
.rank_density = 0x80000000u,
.capacity = 0x80000000u,
.primary_sdram_width = 64,
.ec_sdram_width = 16,
.rdimm = 0,
.mirrored_dimm = 0,
.n_row_addr = 15,
.n_col_addr = 10,
.bank_group_bits = 1,
.edc_config = 2,
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 750,
.tckmax_ps = 1900,
.caslat_x = 0x0001FFE00,
.taa_ps = 13500,
.trcd_ps = 13500,
.trp_ps = 13500,
.tras_ps = 32000,
.trc_ps = 45500,
.twr_ps = 15000,
.trfc1_ps = 350000,
.trfc2_ps = 260000,
.trfc4_ps = 160000,
.tfaw_ps = 21000,
.trrds_ps = 3000,
.trrdl_ps = 4900,
.tccdl_ps = 5000,
.refresh_rate_ps = 7800000,
.dq_mapping[0] = 0x16,
.dq_mapping[1] = 0x36,
.dq_mapping[2] = 0x16,
.dq_mapping[3] = 0x36,
.dq_mapping[4] = 0x16,
.dq_mapping[5] = 0x36,
.dq_mapping[6] = 0x16,
.dq_mapping[7] = 0x36,
.dq_mapping[8] = 0x16,
.dq_mapping[9] = 0x0,
.dq_mapping[10] = 0x0,
.dq_mapping[11] = 0x0,
.dq_mapping[12] = 0x0,
.dq_mapping[13] = 0x0,
.dq_mapping[14] = 0x0,
.dq_mapping[15] = 0x0,
.dq_mapping[16] = 0x0,
.dq_mapping[17] = 0x0,
.dq_mapping_ors = 0,
.rc = 0x04,
};
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