TE9263 的SDRAM调试如何进行

shijiangxiao · 发表于 2010-10-8 14:44:43

我有一个MDK工程，在sram中调试没有问题，在sdram中调试时不稳定。有时不能调。
请问 debug_sdram.ini 配置文件如何编写。

TE9263的晶振采用bypass模式, 不然不能调试, 以下配置是否可以

DEFINE CHAR Setup;
DEFINE INT  Entry;

DEFINE LONG PMC;
DEFINE LONG PIO_SD;
DEFINE LONG MATRIX;
DEFINE LONG SDRAMC;
DEFINE LONG SDRAM;

// Memory mapped peripherals address definitions
PMC = 0xFFFFFC00;
PIO_SD = 0xFFFFF800;
MATRIX = 0xFFFFEC00;
SDRAMC = 0xFFFFE200;
SDRAM  = 0x20000000;

FUNC void __PllSetting()
{
// Disable all PMC interrupt ( $$ JPP)
// AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) //(PMC) Interrupt Disable Register
// pPmc->PMC_IDR = 0xFFFFFFFF;
_WDWORD(0xFFFFFC64,0xFFFFFFFF);
// AT91C_PMC_PCDR  ((AT91_REG *) 0xFFFFFC14) //(PMC) Peripheral Clock Disable Register
_WDWORD(0xFFFFFC14,0xFFFFFFFF);
// Disable all clock only Processor clock is enabled.
_WDWORD(0xFFFFFC04,0xFFFFFFFE);
// AT91C_PMC_MCKR  ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
_WDWORD(0xFFFFFC30,0x00000001);
_sleep_(10);
// write reset value to PLLA and PLLB
// AT91C_PMC_PLLAR ((AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
_WDWORD(0xFFFFFC28,0x00003F00);

// AT91C_PMC_PLLBR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
_WDWORD(0xFFFFFC2C,0x00003F00);
_sleep_(10);

}

//----------------------------------------------------------------------------
//
//    __PllSetting100MHz()
// Function description
//  Set core at 200 MHz and MCK at 100 MHz
//----------------------------------------------------------------------------
FUNC void __PllSetting100MHz()
{
printf( "------------------------------- PLL Set at 100 MHz ----------------------------------\n");

//* pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCBYPASS ));
_WDWORD(0xFFFFFC20,0x00004002); //TE9263需要旁路模式
_sleep_(40);

//* AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA | ((72 << 16) & AT91C_CKGR_MULA) |
// (AT91C_CKGR_PLLACOUNT | (AT91C_CKGR_OUTA_0 | (7);
_WDWORD(0xFFFFFC28,  0x2063BF08); //16M晶振时刚好配置成100M
_sleep_(40);
//* AT91C_BASE_PMC->PMC_MCKR =  AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK / 2 | AT91C_PMC_MDIV;
_WDWORD(0xFFFFFC30,  0x00000006);
_sleep_(40);

}

//----------------------------------------------------------------------------
//    __initSDRAM()
//  Function description
//  Set SDRAM for works at 100 MHz
//----------------------------------------------------------------------------

FUNC void SDRAM_Setup()
{
// Configure PIOs
// AT91F_PIO_CfgPeriph( AT91C_BASE_PIOD, AT91C_PC16_D16 to AT91C_PC16_D31
// pPio->PIO_ASR = periphAEnable; AT91C_PIOC_ASR ((AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
// pPio->PIO_BSR = periphBEnable;AT91C_PIOC_BSR  ((AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
// pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode

// -I- Configure PIOD as peripheral (D16/D31)

_WDWORD(0xFFFFF870,0xFFFF0000);
_WDWORD(0xFFFFF874,0x00000000);
_WDWORD(0xFFFFF804,0xFFFF0000);

// Init MATRIX to support EBI0 CS1 for SDRAM"
// AT91PS_CCFG ((AT91_REG *) 0xFFFFED20) // (CCFG)  EBI0 Chip Select Assignement Register
_WDWORD(0xFFFFED20,0x1000A);

// psdrc->SDRAMC_CR =  AT91C_SDRAMC_NC_9  | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
// AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 |
// AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8 ;

   _WDWORD(0xFFFFE208,0x85227259);
   _sleep_(10);

// psdrc->SDRAMC_MR = 0x00000002; // Set PRCHG AL
_WDWORD(0xFFFFE200,0x00000002);
// *AT91C_SDRAM = 0x00000000; // Perform PRCHG
   _WDWORD(0x20000000,0x00000000);
   _sleep_(10);

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 1st CBR
_WDWORD(0xFFFFE200,0x00000004);

// *(AT91C_SDRAM+4) = 0x00000001; // Perform CBR
_WDWORD(0x20000000,0x00000001);

// psdrc->AT91C_SDRAMC0_MR = 0x00000004; // Set 2 CBR
_WDWORD(0xFFFFE200,0x00000004);
// *(AT91C_SDRAM+8) = 0x00000002; // Perform CBR
_WDWORD(0x20000000,0x00000000);

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 3 CBR
_WDWORD(0xFFFFE200,0x00000004);
// *(AT91C_SDRAM+0xc) = 0x00000003; // Perform CBR
_WDWORD(0x20000000,0x00000000);

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 4 CBR
_WDWORD(0xFFFFE200,0x00000004);
// *(AT91C_SDRAM+0x10) = 0x00000004; // Perform CBR
_WDWORD(0x20000000,0x00000000);

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 5 CBR
_WDWORD(0xFFFFE200,0x00000004);
// *(AT91C_SDRAM+0x14) = 0x00000005; // Perform CBR
_WDWORD(0x20000000,0x00000000);

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 6 CBR
_WDWORD(0xFFFFE200,0x00000004);
// *(AT91C_SDRAM+0x18) = 0x00000006; // Perform CBR
_WDWORD(0x20000000,0x00000000);

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 7 CBR
_WDWORD(0xFFFFE200,0x00000004);
// *(AT91C_SDRAM+0x1c) = 0x00000007; // Perform CBR
_WDWORD(0x20000000,0x00000000);

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_RFSH_CMD; // Set 8 CBR
_WDWORD(0xFFFFE200,0x00000004);
// *(AT91C_SDRAM+0x20) = 0x00000008; // Perform CBR
_WDWORD(0x20000000,0x00000000);

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_LMR_CMD; // Set LMR operation
_WDWORD(0xFFFFE200,0x00000003);
// *(AT91C_SDRAM+0x20) = 0xcafedede; // Perform LMR burst=1, lat=2
_WDWORD(0x20000020,0xcafedede);

// psdrc->AT91C_SDRAMC0_TR = (AT91C_MASTER_CLOCK * 7)/1000000; // Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
// (F : system clock freq. MHz
//_WDWORD(0xFFFFE204,0x000002B7);
_WDWORD(0xFFFFE204, 0x0000030B );

// psdrc->AT91C_SDRAMC0_MR = AT91C_SDRAMC_MODE_NORMAL_CMD; // Set Normal mode
_WDWORD(0xFFFFE200,0x00000000);

// *AT91C_SDRAM = 0x00000000; // Perform Normal mode
_WDWORD(0x20000000,0x00000000);
printf( "------------------------------- SDRAM Done at 100 MHz -------------------------------\n");

}

FUNC void Remap (void) {
  if (Setup & 0x10) {
_WDWORD(MATRIX+0x100,0x00000003); // MATRIX_MRCR: Remap IRAM to 0
_sleep_(100);
  }
}

FUNC void PC_Setup (void) {
  if (Setup & 0x40) {
PC = Entry;
  }
}

FUNC void GoMain (void) {
  if ((Setup & 0xA0) == 0xA0) {
exec("g,main");
  }
}

// <o1.0> Clock Setup
// <o1.1> SDRAM Setup
// <e1.4> Remap
// </e>
// <e1.5> Download Program
FUNC void Download (void) {
  if (Setup & 0x20) {
//  <s0.80> Command for Loading
exec("LOAD debug_sdram\\DebugSdram.axf INCREMENTAL");
  }
}
// </e>
// <e0.6> Setup Program Counter to Entry Point
// <o1> Program Entry Point <0x0-0xFFFFFFFF>
// </e>
// <e.7> Execute Program untill Main Function
// </e>
Setup = 0x7F;
Entry = 0x20000000;

__PllSetting();                //* Init PLL
__PllSetting100MHz();
SDRAM_Setup();
Remap();
Download();
PC_Setup();
GoMain();

飞凌-fatfish · 发表于 2010-10-8 17:15:00

帮顶一下，没碰到过。